Lab2 Pipelining
(1) Understand Basic Concepts of Computer Pipeline
(2)Understand how MIPS is implemented with five pipelines, and understand the functions and basic operations of each segment.
The experimental platform adopts instruction level and pipeline operation level simulator MIPSsim.
First of all, we should master the use of MIPSsim simulator.
(1)Start MIPSsim
(2)According to the description of pipeline operation in the preliminary knowledge, further understand the function of each segment in pipeline window and grasp the meaning of each pipeline register.(Double-click each segment with the mouse, and you can see the contents of each pipeline register.)
(3)Familiar with the operation and use of MIPSsim simulator.
You can first load a sample program (in the “sample program” folder under the folder where the simulator is located), then run the program in the way of single-step execution of a cycle, execution of multiple cycles, continuous execution, setting breakpoints, etc., observe the execution of the program, observe the changes of the contents of registers and memories in the CPU, especially the change of
contents of pipeline registers.
(4)Select the “Pipelining” option in the configuration menu to make the simulator work in pipelining mode.
(5)To observe the program execution in the pipeline, the steps are as follows:
1Select MIPSsim’s “File” ¡ú”Load Program” option to load pipeline.s (in the “Sample Program” folder under the folder where the simulator is located).
2 Turn off the forwarding function. This is achieved by “configuration”¡ú “forwarding” (so that there is no ¡Ì before the item).
3 The program is executed in a single cycle (in the “Execution” menu) or by pressing the F7 key. Observe the changes in the contents of pipelining registers, the execution of instructions (code window) and 1
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the clock cycle diagram in each cycle.
4When the 13th clock cycle is executed, the instructions being processed by each segment are:
IF: ID: EX: ME WB:
5Draw the clock cycle diagram at this time.
6Analysis these instructions¡¯ execution at this time.
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(6)At this time, the contents of each pipeline register are (in hexadecimal representation): 1F/ 1D. IR ,
IF/ ID. NPC,
ID/ EX. A :
ID/ EX. B:
ID/ EX. Imm :
ID/ EX. IR:
EX/ MEM. ALUo: EX/ MEM. IR:
ME M/ WB. LMD: MEM / WB. ALUo : MEM / WB. IR:
2.4 Questions
(1) What is Pipeline Register
(2) Compare the advantages and disadvantages of the three processor implementation styles: single cycle, multi-cycle and pipeline implementation
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