Sigma-Delta Data Converters
Laboratory Session 3
1.0 Objectives
This laboratory comprises 2 sets of exercises.
In the first set of exercises, we will study the properties of third order modulator topologies.
Modulators with noise-shaping order > 2 can be unstable for some or even all possible
inputs, usually displaying chaotic limit cycle behaviour unrelated to the input signal when
unstable. We will see that careful architecture selection for single-loop modulators, which
entails controlling the form of NTF to limit its maximum gain and hence noise levels in the
loop and using multi-bit quantisation can both be used to improve high order modulator
stability and increase the stable input range.
In laboratory 5 we will look at another approach to creating stable high-order modulators
based on cascading stable low-order modulators. You will refer back to many of the results
from this laboratory in laboratory 5, so you are strongly encouraged to keep good notes of
your results for this laboratory!
In the second set of exercises, you will learn how to use a widely-used, MATLAB-based
Sigma-Delta Toolbox to synthesise NTFs to meet a given SQNR target and then generate
coefficients for some generic higher order modulator structures capable of realising those
NTFs as circuits or code (like Simulink). This toolbox was written by one of the course text
authors (Schreier) and is described in depth in the text [1]. Four different modulator
structures are supported by the toolbox: Cascaded Integrators FeedBack (CIFB),
Cascaded Integrators FeedForward (CIFF), Cascaded Resonators FeedBack (CRFB),
Cascaded Resonators FeedForward (CRFF). See page 128-134 of [1] for a derivation and
analysis of these structures.
You may wish to consult the course textbook as you are following the laboratory,
“Understanding Delta Sigma Modulators” By R. Shreier and G. Temes, which is available
online at:
http://ieeexplore.ieee.org/xpl/bkabstractplus.jsp?bkn=5264508
You should still have a copy of all the Matlab laboratory materials in a directory called
“EdUni” created at the start of Laboratory 1; if not then please consult the laboratory 1
hand-out for instructions on how to create this Matlab.
Change directory into this location by typing “cd EdUni”.
In this directory there are general utility routines:
sweep_testbench.mdl
In the directory “LAB3” there are a number of files that will be used in this exercise:
MakeModulator.m
mod3_4bit.slx
mod3_crff_1bit.mdl
mod3_crff_2bit.mdl
mod3_crff_3bit.mdl
mod3tb_cifb_1bit.mdl
mod3tb_cifb_2bit.mdl
mod3tb_cifb_3bit.mdl
mod3tb_cifb_3bitTBQ.mdl
mod3tb_ciff_2bit.mdl
mod3tb_crfb_2bit.mdl
mod3tb_crff_2bit.mdl
mod4tb_cifb_3bit.mdl
plotpoles.m
As in laboratory sessions 1 and 2, we will also require the utilities held in the directory
“ELEE11080_ROUTINES”.
The directory ‘delsig’ contains the toolbox files, which we will be using in this lab.
Note: The Sigma-Delta toolbox can be freely downloaded from The Mathworks website;
link below http://www.mathworks.co.uk/matlabcentral/fileexchange/19-delta-sigma-toolbox.
In the top-level directory “EdUni”, start Matlab by typing “matlab” in the shell window.
In Matlab, right click on the directory name “ELEE11080_ROUTINES” in the Current
Folder pane on the left. Select the option “Add to Path > Selected Folders and
SubFolders”. Do the same for the directories “LAB3” and “delsig”.
Type “init_vars3” into the Matlab Command Window. This routine sets the default values
for common variables used in the various forthcoming exercises (it is identical to “init_vars”
used in previous laboratories except it selects the Blackman-Harris window in the “psdctrl”
structure for computing power spectral densities. Do not use a Hann window in this
laboratory as the default settings will give SQNR estimates corrupted strongly by the
window skirts.)
You are now ready to begin the lab 3 exercises set 1.
1.2 Third Order Modulator Simulink Model
Fig. 1 mod3.mdl schematic
Right-click on “mod3.mdl” in “LAB3” and select “Open F4”. You should now see the third
order modulator schematic (MOD3) shown in Figure 1. This modulator is obtained from
MOD2 in the same way as MOD2 was derived from MOD1 – by replacing the quantiser
with another MOD1 – and consists of the following main elements:
1. Three non-delaying integrators each composed of a 1/z unit delay element in
feedback to an adder. Descending into any of the integrator blocks you will see a
gain block precedes the delay element and can represent any finite integrator gain
at dc, and a saturation block represents the clipping effect of, e.g., finite power
supply voltages or digital word lengths in real modulators. Further details were
given in the lab 1 notes. The integrators are the core blocks responsible for noise
shaping in the modulator.
2. A midrise quantiser. This is a single-bit quantiser with output states -1 and 1 as
described in the lab 1 notes and used in labs 1 and 2.
3. A delaying feedback loop from the quantiser output to the input, where the two
signals are subtracted and the error signal LOOPERR is applied to the integrator.
The delay in the feedback represents the time to quantise, sample and feed back
the integrator output – usually a single clock cycle.
4. A random dither source input scaled by a gain block modctrl.dgain1 (default 0: no
dither) applied at the input of the quantiser.
The default sampling frequency, Fs, is chosen as 1MHz. The default oversampling ratio,
OSR, is 64. The signal band of interest extends to Fs/(2.OSR), i.e. from 0 Hz to 7812.5 Hz.
1.3 MOD3 Time Domain Operation for DC Input
We will now examine how the third order modulator sigma-delta ADC behaves with a DC
input. You may wish to compare with your results for MOD1 and MOD2 dc behaviour from
labs 1 and 2.
Close “mod3.mdl” then open “sweep_testbench.mdl” and right click on the block marked
“dut”. Edit “model reference parameters” to “mod3.mdl” and then double click on the block
to open the mod3.mdl schematic from within the test bench. Now double click on any one
of the small pairs of blue icons by each of the integrator or quantiser outputs to open the
time waveform viewer scope.
Set the DC input level to 0 by typing “input_dc = 0” into the Matlab command window or by
right clicking on the input_dc entry in the workspace pane and editing its value to 0.
Select the dc test source in the test bench by typing “swpctrl.select = 2” in the Matlab
Command Window and then run the simulation by selecting “Simulation > Start” or
pressing
You will see the integrator and quantiser outputs appear in the time scope window.
Click on autoscale (binoculars icon) to scale the integrator and quantiser waveforms.
1. Does the quantiser output follow a repeating limit cycle as seen for MOD1 and
MOD2 with rational dc input levels (and no dither)?
2. Comment on the integrator outputs, in particular note their magnitudes and the
scales of the axes.
3. What does this tell you about the stability of this basic MOD3 modulator? Recall the
idea of BIBO (bounded input bounded output) stability – do the integrator outputs
appear bounded? So is the modulator stable?
No limit cycle is seen in the quantiser output. Observing the integrator outputs reveals the
modulator to be unstable: the amplitude of the outputs grows unboundedly.
Now, try re-running the simulation for a few other input levels for input_dc such as “–pi/10”
and “+0.4367”.
1. Can you find any input that doesn’t make the integrator outputs grow unboundedly?
So is this modulator stable, conditionally stable, or completely unstable? (Don’t
spend more than a minute or two on this, just try a few input levels and draw a quick
conclusion.)
The basic MOD3 modulauor is completely unstable, regardless the input.
We will not focus on the details of modulator stability during the laboratory, but after the
laboratory you are encouraged to read and try the material in Appendix 1 which explains
why this modulator is unstable; this appendix covers some very general concepts that
underpin most modulator stability/instability cases.
1.4 An Improved Third-order CRFF DSM Loop with DC Input
The previous exercise highlighted that basic MOD3 is completely unstable with dc inputs.
You should not be surprised to learn it is unstable with sine wave inputs (you could try this
later) or indeed any useful input signal. This does not mean however that all third and
higher order modulators are completely unstable. Various (sometimes heuristic)
techniques exist for creating (possibly) stable high order modulators, some of which, and
the reasons behind them, are covered in the lectures and course text.
Close the “mod3.mdl” window and the timescope if they are still open. You should still
have “sweep_testbench.mdl” open.
Now right click on “dut” in the “sweep_testbench.mdl” schematic and edit the model
reference parameters to “mod3_crff_1bit.mdl”.
Double click on the dut component to see the new modulator architecture, which is of the
type “CRFF” discussed in section 4.4 and appendix B of [1], and uses additional
feedforward paths to the quantiser input to modify the NTF to aid stability.
Note that integrators 1 and 3 are now delaying integrators; double click on integrators 1
and 2 to see their internal schematics and compare. Note also that compared to MOD3 the
feedback paths returns only to the first integrator input and has no delay.
This example uses architectural modification (the feedforward paths to the summer before
the quantiser) to change the loop NTF from
• NTF = (1-z-1)3 = (z-1)3 / z3 (basic MOD3)
• NTF = (z-1)3 / (z-0.5903)(z2 – 1.363z + 0.5792) (new modulator)
Note that the 3 NTF poles (highlighted in red) have been moved from all at z=0 to all
closer to z=1 for the new modulator. Note also that both NTFs still have the same 3 zeros
at dc (z=1) that are responsible for the 3rd-order noise shaping. Figure 2 compares the
magnitude responses of these NTFs.
Fig. 2 Comparison of the basic MOD3 and CRFF-modified MOD3 NTFs.
Two important differences between the NTF magnitude responses to note are:
• The maximum NTF gain (at Fs/2, i.e. at z=-1) is reduced to x1.71 (4.6 dB) from x8
• The signal-band (low frequency) NTF is now 21dB higher than the basic MOD3
Reducing the maximum gain reduces the level of high-frequency noise at the quantiser
input. High levels of quantiser input noise can badly saturate the quantiser and the
resulting change in effective quantiser gain can cause NTF poles outside the unit circle,
causing instability (see Appendix 1 for an illustration of this). Reducing the noise level can
thus enable stable operation.
The penalty for achieving stability is that while the new NTF has lower gain at high
frequencies, the gain is now 21 dB higher in the signal pass-band (exercise: now confirm
this 21 dB low-frequency NTF increase by hand calculation; you should be able to do it
very easily if you notice that the NTFs given above differ only in their denominators/poles –
so choose the right frequency to compare the NTF denominators at).
The ratio of the NTF is r=(z-0.5903)(z2 – 1.363z + 0.5792)/z3
Evaluating this at DC (z=1) gives r=(1-0.5903)(1-1.363 + 0.5792)=0.088577,
or expressed in decibels: r=20log10(0.088577)=-21.054dB -> MOD3 NTF is 21dB is lower
Since the signal-band NTF is 21 dB higher than MOD3’s then 21 dB more in-band
quantisation noise will result, i.e. SQNR for a given signal will be about 21 dB less than a
true (1-z-1)3 NTF modulator could achieve; this reduced maximum achievable SQNR is the
cost we pay here for achieving stability in our 3rd order modulator loop.
(Notes: Note that it is impossible to reduce the high-frequency NTF gain without
increasing the NTF gain at lower frequencies. This follows directly from the Gerzon-Craven
equal-areas theorem illustrated in Figure 3:
Fig. 3 Illustration of the equal areas theorem.
This theorem follows directly from a result from complex analysis showing that – on a log
gain axis – areas A and B must be equal for physically realizable noise transfer functions.
There is thus a fundamental trade-off between stability and achievable SQNR. Any attempt
to reduce high frequency NTF gain to aid stability will reduce area B and so area A must
reduce correspondingly. Area A can only reduce by raising the NTF curve towards 0 dB,
i.e. by having more quantisation noise at low frequencies and hence obtaining a lower
maximum possible SQNR.)
Double click on one of the blue timescope icons in “mod3_crff_1bit.mdl” to open the time
scope. Set “input_dc = 0” and then run the simulation by selecting “Simulation > Start” or
pressing
type “mean(Qout)” to see the mean/dc value of the modulator output and “Qout_SNDR” to
see the output spectrum.
1. Observe the integrator outputs. Are they now bounded? Is the modulator stable?
2. Compare the mean modulator output with input_dc? Are they a good match? Has
the modulator implemented a dc accurate analogue to digital conversion; i.e. what
sort of error do you see between input_dc and mean(Qout)?
3. Zoom in on a few cycles of Qout and look also at the output spectrum. Is this
modulator tonal for dc input 0 as seen with MOD2 and MOD1?
input_dc=0
101 102 103 104 105 106
Frequency(Hz)
Modulator output spectral density (Units/sqrt(Hz))
Brickwall LPF @ fs/(2.OSR)
Simulated:
SQNR = -8.4 dB
ENOB = -1.7
The integrator outputs are now bounded, so the modulator is stable, and the mean
modulator output matched the input level (0) exactly. As with MOD1 and MOD2, the
behaviour is again tonal, with tones at 125KHz and 375kHz (however, just as with MOD1
and MOD2 the tones are well outside the signal band).
Repeat the above exercise for input_dc values from +0.2 to +0.6 in increments of 0.2 and
then to +1.0 in increments of 0.1.
1. Does the modulator stay stable for all inputs up to the maximum possible full-scale
limit of +1? If not then roughly what is the stable dc input range (do not try finding
this to high accuracy, +/- 0.05 is accurate enough)? Note the integrator output
signal ranges as the stable limit is approached. What happens to them?
2. Is the modulator an accurate converter for dc inputs inside the stable input range?
3. Is this modulator tonal for rational dc inputs in its stable input range (as seen for
MOD1 and MOD2 in previous labs)? How could you address this if it could be a
input_dc=0.2
input_dc=0.4
input_dc=0.6
input_dc=0.7
input_dc=0.75
input_dc=0.8 (similar plots are obtained for input_dc=0.9)
input_dc=1
The modulator becomes unstable between input_dc=0.75 and input_dc=0.8, the amplitude
of INT3OUT growing rapidly as the stabe limit is approached. Within the stable input
range, the modulator is an accurate coverter for DC inputs (as far as the mean value of
Qout is concerned, however it is still possible to get in-band limit cycles for some input
levels, try, e.g., input_dc=0.01!). Just as with MOD1 and MOD2, certain rational DC inputs
will lead to in-band tones, so it is prudent to use some dither to avoid problem inputs (this
is in fact true for any modulator structure!).
We note that although the modulator appears to be stable for input_dc=1, in practice any
small disturbance (even thermal noise) would throw off the modulator and lead to the
integrator outputs becoming unbounded.
Recall from previous laboratories that for analogue modulators where the integrators may
have a finite dc gain “A”, MOD1 required very high gain to minimise dead zones (its dead
zone width is proportional to 1/A) and MOD2 was much more tolerant of low gains as the
two integrator gains are multiplied before the input reaches the quantiser (dead zone width
is proportional to 1/A2).
We will now examine the tolerance of our stable third-order modulator to dc gain.
Close all Simulink windows and type “target_modulator=’mod3_crff_1bit’” and then run
“sweep_dc_dc” to obtain a dc transfer function of the modulator for dc inputs around zero
with ideal integrators having infinite dc integrator gains (default settings from “init_vars3”).
Do not close this window for now and keep a copy of this transfer function plot for later.
Then set the dc gain of all integrators to 10 by typing “modctrl.igain1=10”,
“modctrl.igain2=10” and “modctrl.igain3=10” and then run “sweep_dc_dc” again and
compare the results. Again, please keep a copy of this plot.
1. Compare the dc transfer functions obtained with ideal integrators and integrators
with gain 10. Are any dead zones visible at the sweep resolution (steps of 0.001)? If
so then how do they compare with MOD1 and MOD2 with these integrator gains (if
you do not have these results in your lab book and need to re-run the MOD1 and
MOD2 results then remember to add LAB1 and LAB2 to your Matlab path and set
“target_modulator” to “’mod1’” or “’mod2’” before running “sweep_dc_dc”).
2. Note the width of the dead zone centred on dc input 0.
-0.1 -0.08 -0.06 -0.04 -0.02 0 0.02 0.04 0.06 0.08 0.1
Modulator dc transfer function around dc = 0.000
for modulator mod3
IGAIN=inf IGAIN=10
The deadzones are considerably smaller than in the case of MOD1 and MOD2, only the
deadzone around input_dc=0 (with width 0.006) is readily visible, it is only when one
zooms into the plot that small deadzones (around simple rational inputs) can be seen.
Reduce the gain of all integrators identically from 9 to 4 in steps of -1 (i.e. gains 9,9,9 then
8,8,8 etc.) and note the widths of the dead zone around 0 input in each case.
1. What power of the gain does the width of the dead zone around input_dc=0 depend
on? Is this what you would expect intuitively?
2. Is achieving high enough dc integrator gain to supress dead zones likely to be a
major issue for real implementations of this type of third-order (or higher-order)
modulator design?
The width of the deadzone is seen to be (approximately) proportional to 1/A^3 (the power
of 3 arising from the order of the modulator). Thus the size of the dead zone will diminish
rapidly as A is increased and is likely to be insignificant for practical values of A.
1.5 CRFF Third-order Loop with Sine Wave input.
Close all Simulink windows except “sweep_testbench.mdl” (open it if it is not already open)
and ensure the Model Reference Parameter of dut is set to “mod3_crff_1bit.mdl”. Select
the sine wave input of “sweep_testbench.mdl” by typing “swpctrl.select = 1” in the Matlab
Command Window. As before, the workspace variable “sinamp” sets the amplitude of this
sine wave and “sinfreq” sets the frequency.
Reset all integrator gains to +inf (a quick way to do this is to execute “init_vars3” again in
the command window).
Set “sinamp = 0.1” and “sinfreq = 4882.8125” if they are not already set to these values.
Run the simulation by selecting “Simulation > Start” or pressing
“sweep_testbench.mdl” window. Once complete, type “Qout_SNDR” in the Matlab
Command Window to see the modulator output spectrum and simulated SQNR.
1. Estimate the slope of the output spectrum in the passband? Is this what you would
expect? Why?
2. Note the reported signal to noise ratio given by “Qout_SNDR” and compare it to the
theoretical maximum given by the formula:
(log10)(log)1020(76.1.02.6
where the modulator order L=3, the oversampling factor OSR=64, and number of
→ Recall that this is the theoretical SQNR for a full-scale input sinamp = 1 (i.e. 0
dB). We have used sinamp = 0.1 (-20 dB), so modify your calculation appropriately
when comparing.
→ Recall also the comment at the start of section 1.4 about the 21 dB passband
penalty incurred by modifying the NTF to achieve stability and note that the above
formula applies only for a (1-z-1)L NTF.
3. How does the simulated SQNR compare with those obtained previously for MOD2
and MOD1? Does this modulator give worse, comparable, improved, or much
improved SQNR at this OSR?
101 102 103 104 105 106
Frequency(Hz)
Modulator output spectral density (Units/sqrt(Hz))
Brickwall LPF @ fs/(2.OSR)
Simulated:
SQNR = 70.7 dB
ENOB = 11.4
Slope in the passband is 60dB/dec, which is consistent with the order of the modulator
(3×20=60dB/dec for a 3rd order modulator).
The SQNR predicted by theory is 112.8dB-20dB-21.1dB = 71.1dB (which is very close to
the 70.7dB observed in the above simulation).
Note that the SQNR is 18dB higher than what we saw with MOD1, and similar to that for
MOD2, despite the input amplitude being 17dB lower.
Repeat the above exercise for “sinamp = 0.8”.
1. Explain your result. You may wish to look at the time domain waveforms using the
time scope (double-click on dut and then the blue icons as before then re-run) and
comment on the integrator outputs.
101 102 103 104 105 106
Frequency(Hz)
Modulator output spectral density (Units/sqrt(Hz))
Brickwall LPF @ fs/(2.OSR)
Simulated:
SQNR = -23.9 dB
ENOB = -4.3
The SQNR has collapsed as the modulator has become unstable, due to sinamp=0.8
being beyond the modulator’s stable input range.
Close all windows and type “target_modulator = ‘mod3_crff_1bit’” in the Matlab Command
Obtain a plot of SQNR versus input amplitude by running “sweep_sin_ampl_sqnr”. You
should make a copy of this plot for reference in the next section.
1. Note the amplitude giving maximum SQNR and compare this to the maximum
stable dc_input. Are they roughly the same? Would you expect this, i.e. is the
maximum stable dc input generally a good indicator of the maximum stable sine
amplitude?
2. Make a note of the maximum SQNR value.
The amplitude giving maximum SQNR is -5dBFS = 10^(-5/20) = 0.56. This is somewhat
below the maximum stable sine amplitude of 10^(-3/20) = 0.707, which is in turn consistent
with the maximum stable dc input identified in section 1.4 above (this is not surprising: as
soon as the instantaneous value of an input sinewave exceeds the stable dc input, then
instability is expected to occur). The maximum SQNR is 84.9dB.
1.6 CRFF Third-Order Loop with Multi-bit Quantisation.
The previous exercises examined stability issues in high-order loops and demonstrated
how a stable 3rd order modulator could be constructed by using different loop architectures
than basic MOD3; in this case a “CRFF” architecture. However, this CRFF modulator is
only stable for inputs in the range of (approximately) [-0.7:0.7]. One other way we can
often further improve loop stability and extend the stable input range is to progress from
using a single-bit quantiser and feedback path to multi-bit quantisation and feedback.
Multi-bit quantisers have better defined gain than single-bit quantisers as more than 2
points define the slope of the quantiser input/output characteristic (i.e. effective gain); you
may recall this from the quantiser gain exercises from lab 1 if you had time to try them.
See also sections 2.1.1 and 6.1 of [1].
Close the Simulink windows from the previous section except for “sweep_testbench.mdl”
and the output of “sweep_sin_ampl_sqnr” (or, better, make a hard copy of it as you will
need to refer back to it shortly).
Right click on “dut” in “sweep_testbench.mdl” and edit the model reference parameters to
“mod3_crff_2bit.mdl”.
Double click on the dut to see the modulator schematic. This looks the same as in the
previous exercise, but now the 1-bit quantiser with output step size 2 (-1 to +1) has been
replace with a 2-bit quantiser with step size 2/3 (switching thresholds -2/3, 0 and +2/3 and
output levels -1, -1/3, +1/3 and +1). You can double-click on the quantiser to see what has
been changed.
Double click on any of the blue icons to open the time scope for the integrator and
quantiser outputs.
Reset the sine wave and dc inputs by typing “sinfreq = 4882.8125”, “sinamp = 0.707” and
“input_dc = 0” and then run the simulation by selecting “Simulation > Start” or pressing
Type “Qout_SNDR” to see the modulator output spectrum. Use the magnifying glass to
zoom in on the 2-bit quantiser output in the time-scope view and note how it resembles the
sine wave much more obviously than in the 1-bit case.
1. Estimate and comment on the slope of the SQNR graph; is it still what you would
2. Note the reported signal to noise ratio given by “Qout_SNDR” and compare it to the
theoretical maximum given by the formula:
(log10)(log)1020(76.1.02.6
where the modulator order L=3, the oversampling factor OSR=64, and number of
bits N=2. Recall that this is the theoretical OSR for a full-scale input sinamp = 1
(0dB). We have used sinamp = 0.707 (-3 dB), so modify your calculation
appropriately when comparing and again recall the NTF penalty comment from
The slope of the spectrum in the passband is still ≈60dB/dec, as expected (given that the
order of the modulator has not changed).
The SQNR predicted by theory is 118.9dB-3dB-21.1dB = 94.8dB (which is similar to the
96.6dB observed in the above simulation, the small discrepancy could be due to
inaccuracies in the simulated spectrum and extraction of SQNR).
Close all Simulink windows and obtain a plot of SQNR versus input amplitude by typing
“target_modulator=’mod3_crff_2bit’” and then running “sweep_sin_ampl_sqnr”. Compare
your results with those obtained for the 1-bit quantisation case.
1. What is the maximum SQNR level? How does this compare with the 1-bit case?
2. At what amplitude is the maximum SQNR obtained? Has the stable input range
improved compared to the CRFF with 1-bit quantisation?
3. Compare the SQNR of the 1-bit and 2-bit modulators for a selection of inputs within
their stable ranges, e.g. -10, -30 and -40 dB relative to full-scale (dBFS). Are they
the same? Has adding the extra quantiser bit only extended the 1-bit plot to higher
stable inputs, or has it also improved SQNR for all inputs? If so then why would this
happen (don’t spend too long on this, ask a demonstrator for comment)?
The max SQNR is 97.7dB, compared with 84.9dB in the 1-bit case. This increase is
greater than the 6.02dB increase expected by adding a single bit to the quantiser (and the
resulting reduction in step size), due to the stable input range having been expanded.
The amplitude giving maximum SQNR is now -2dBFS = 10^(-2/20) = 0.79, and the
maximum stable sine amplitude is at least 10^(-1/20) = 0.89 (c.f. 0.707 in 1-bit case).
The SQNR has improved for all input amplitudes (by around 10dB for most of the input
Now select a 3-bit (8 levels) quantiser by typing “target_modulator = ‘mod3_crff_3bit’”, this
has a quantiser with equally spaced input switching thresholds at (-6/7, -4/7, -2/7, 0, 2/7,
4/7, 6/7) and outputs levels (-1, -5/7, -3/7, -1/7, 1/7, 3/7, 5/7, 1).
Re-run the sweep “sweep_sin_ampl_sqnr” and compare with the 1-bit and 2-bit
quantisation cases.
Open “sweep_testbench.mdl” if it is not already open. Set “sinamp = 0.95” and double click
on dut in “sweep_testbench.mdl” and then double click any of the blue icons to activate the
time scope. Run the simulation by selecting “Simulation > Start” or pressing
“sweep_testbench.mdl” window.
1. How far does the stable input range extend now compared to the 1-bit and 2-bit
modulators?
2. How does the peak SQNR for the modulator with a 3-bit quantiser compare with that
estimated using the formula
(log10)(log)1020(76.1.02.6
Remember to account for the NTF penalty and the signal amplitude at peak SQNR.
3. How does the SQNR versus amplitude plot compare with the 1-bit and 2-bit cases?
Explain the differences.
4. Zoom in on a few cycles of “quantout” in the time-scope for sinamp = 0.95. Can you
see how this 3-bit DSM tracks even more closely the large input sine wave using all
8 quantiser levels?
The modulator is now stable for sine amplitudes up to 1 (it is only barely stable at 1), peak
SQNR being achieved at an amplitude of around 10^(-1/20) = 0.89.
The SQNR predicted by theory is 124.9dB-1dB-21.1dB = 102.8dB (which is broadly similar
to the 107.4dB observed in the above simulation, the discrepancy could be due to
inaccuracies in the simulated spectrum and extraction of SQNR).
Compared to the 2-bit case, not only has the stable input range being extended, the SQNR
has been raised for all input amplitudes (by an amount commensurate with the 6.02dB
gain expected from the additional bit of resolution added t