ECE 6913 RISC V Project A

Computer Architecture 体系结构代写, Optimization 优化代写 / C++ 代写, python 代写, RISC-V 代写

Performance Modelling – RISC-V processor
This project will require you to implement cycle-accurate simulators of a 32-bit RISC-V processor in C++ or Python. The skeleton code for the assignment is given in le (NYU_RV32I_6913.cpp or NYU_RV32I_6913.py).
The simulators should take in two les as inputs: imem.text and dmem.txt les The simulator should give out the following:
¡ñ cycle by cycle state of the register le (RFOutput.txt)
¡ñ Cycle by cycle microarchitectural state of the machine (StateResult.txt)
¡ñ Resulting dmem data after the execution of the program (DmemResult.txt)
The imem.txt le is used to initialize the instruction memory and the dmem.txt le is used to initialize the data memory of the processor. Each line in the les contain a byte of data on the instruction or the data memory and both the instruction and data memory are byte addressable. This means that for a 32 bit processor, 4 lines in the imem.txt le makes one instruction. Both instruction and data memory are in ¡°Big-Endian¡± format (the most signicant byte is stored in the smallest address).
The instructions to be supported by the processor are categorized into the following types:
The simulator should support the following set of instructions.
Psuedocode
rd=rs1+rs2
Store the result of rs1 + rs2 in register rd.
Subtraction
rd=rs1-rs2
Store the result of rs1 – rs2 in register rd.
Bitwise XOR
rd=rs1^rs2
Store the result of rs1 ^ rs2 in register rd.
Bitwise OR
rd=rs1|rs2
Store the result of rs1 | rs2 in register rd.

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Bitwise AND
rd=rs1&rs2
Store the result of rs1 & rs2 in register rd.
Add Immediate
rd = rs1 + sign_ext(imm)
Add the sign-extended immediate to
register rs1 and store in rd. Overow bits ignored.
XOR Immediate
rd = rs1 ^ sign_ext(imm)
Bitwise XOR the sign-extended immediate to register rs1 and store result in rd.
OR Immediate
rd = rs1 | sign_ext(imm)
Bitwise OR the sign-extended immediate to register rs1 and store result in rd.
AND Immediate
rd = rs1 & sign_ext(imm)
Bitwise AND the sign-extended immediate to register rs1 and store result in rd.
Jump and Link
PC = PC + sign_ext(imm)
Jump to PC = PC + sign_ext(imm) and store the current PC + 4 in rd.
Branch if equal
PC=(rs1==rs2)?PC+ sign_ext(imm) : PC + 4
Take the branch (PC = PC + sign_ext(imm)) if rs1 is equal to rs2.
Branch if not equal
PC=(rs1!=rs2)?PC+ sign_ext(imm) : PC + 4
Take the branch (PC = PC + sign_ext(imm)) if rs1 is not equal to rs2.
rd = mem[rs1 + signa(imm)][31:0]
Load 32-bit value at memory address [rs1 + signPext(imm)] and store it in rd.
Store Word
data[rs1 + sign_ext(imm)][31:0] = rs2
Store the 32 bits of rs2 to memory address [rs1 value + sign_ext(imm)].
Halt execution
Instruction encoding:
Bit Fields
31:27 26:25

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imm[20|10:1|11|19:12]
imm[12|10:5]
imm[4:1|11]
imm[12|10:5]
imm[4:1|11]
The simulator should have the following ve stages in its pipeline:
¡ñ Instruction Fetch: Fetches instruction from the instruction memory using PC value as address.
¡ñ Instruction Decode/ Register Read: Decodes the instruction using the format in the table above
and generates control signals and data signals after reading from the register le.
¡ñ Execute: Perform operations on the data as directed by the control signals.
¡ñ Load/ Store: Perform memory related operations.
¡ñ Writeback: Write the result back into the destination register. Remember that R0 in RISC-V can
only contain the value 0.
Each stage must be preceded by a group of ip-ops to store the data to be passed on to the next stage in the next cycle. Each stage should contain a nop bit to represent if the stage should be inactive in the following cycle.
The simulator must be able to deal with two types of hazards.
1. RAW Hazards: RAW hazards are dealt with using either only forwarding (if possible) or, if not, using stalling + forwarding. Use EX-ID forwarding and MEM-ID forwarding appropriately.
2. Control Flow Hazards: The branch conditions are resolved in the ID/RF stage of the pipeline.
The simulator deals with branch instructions as follows:
1. Branches are always assumed to be NOT TAKEN. That is, when a beq is fetched in the IF stage, the PC is speculatively updated as PC+4.
2. Branch conditions are resolved in the ID/RF stage.

3. If the branch is determined to be not taken in the ID/RF stage (as predicted), then the pipeline proceeds without disruptions. If the branch is determined to be taken, then the speculatively fetched instruction is discarded and the nop bit is set for the ID/RR stage for the next cycle. Then the new instruction is fetched in the next cycle using the new branch PC address.
1) Draw the schematic for a single stage processor and ll in your code in the to run the simulator. (20 points)
2) Draw the schematic for a ve stage pipelined processor and ll in your code to run the simulator. The processor should be able ot take care of RAW and control hazards by stalling and forwarding. (20 points)
3) Measure and report average CPI, Total execution cycles, and Instructions per cycle for both these cores by adding performance monitors to your code. (Submit code and print results to console or a le.) (5 points)
4) Compare the results from both the single stage and the ve stage pipelined processor implementations and explain why one is better than the other. (5 points)
5) What optimizations or features can be added to improve performance? (Extra credit 1 point)
Your work will be evaluated against the 10 test cases, 3 of which will be revealed one week before the deadline. (50 points – 5 points each)
Useful References:
¡ñ More details on the full ISA specication can be found at
https://riscv.org/wp-content/uploads/2019/12/riscv-spec-20191213.pdf
¡ñ bitset library for C++: https://en.cppreference.com/w/cpp/utility/bitset
¡ñ g++: https://gcc.gnu.org/onlinedocs/gcc-3.3.6/gcc/G_002b_002b-and-GCC.html
¡ñ python: https://www.python.org/downloads/

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