《 Computer Architecture — CPU Logisim HW》
1. HWDescription
Your task is to develop the CPU 250/16, which is a RISC (Reduced Instruction Set Computing) architecture that resembles MIPS, but is word-addressed and uses 16-bit words instead of byte-addressing. To complete this task, a single cycle implementation of the architecture will be designed using Logisim. The specifications for the CPU are listed in the provided Table.
● Logisim implementations must use only the components specified in the “Logisim restrictions”
section later in this document.
● For successful automated grading, your circuit must meet the requirements specified in the
“Automated testing” section.
● You may not use any pre-existing Logisim circuits (i.e., that you could possibly find by searching
the internet).
A. CPU250/16 Instruction Set:
Instruction
lw $rt, D($rs)
$rt = Mem[$rs+D]
sw $rt, D($rs)
Mem[$rs+D] = $rt
beq $rs, $rt, B
if ($rs==$rt) then PC=PC+1+B; else PC=PC+1
bgt $rs, $rt, B
if ($rs>$rt) then PC=PC+1+B; else PC=PC+1
(upper 4 bits zeroed)
$r7=PC+1; PC = L
$rt = keyboard input
output $rs
print $rs on a TTY display
add $rd, $rs, $rt
$rd = $rs + $rt
addi $rt, $rs, Imm
$rt = $rs + Imm
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sub $rd, $rs, $rt
sll $rd, $rs,
$rd = $rs << shamt (shamt is unsigned)
srl $rd, $rs,
$rd = $rs >> shamt (logical shift: no special treatment of sign bit; shamt is unsigned)
and $rd, $rs, $rt
$rd = $rs & $rt
xor $rd, $rs, $rt
$rd = $rs XOR $rt
B. AboutR,IJInstructionTypes:
The R, I, and J type instructions are presented below, indicating the number of bits used for each instruction type within parentheses. The specific bit numbers for each instruction type are also provided in brackets, keeping in mind that the rightmost bit is referred to as bit 0.
Immediate values are represented using 6 bits in signed 2’s complement format, and must be sign-extended.
The input instruction operates in a nonblocking manner, meaning that it always completes and writes a value into the destination register.
– When data is read, bits 15-8 of $rt ($rt[15..8]) must always be set to 0.
– If valid data is retrieved from the keyboard, $rt[7] should be 0, and $rt[6..0]
should represent the 7-bit value that was read.
– If valid data is not available on the keyboard, $rt[7] should be 1, and $rt[6..0]
should be set to 0.
– As a result, $rt should contain the ASCII code that was read from the keyboard,
or 128 to indicate that no data was available. The keyboard input device available in Logisim will be used.
The output instruction writes a 7-bit ASCII character contained in the lower 7 bits of $rs ($rs[6..0]) to the Logisim TTY output device. The TTY should be configured with 13 rows, 80 columns, and operate on the rising edge.
2. Registers
CPU 250/16 has 8 general purpose registers: $r0-$r7
– The register $r7 is the link register for the jal instruction (similar to $ra in MIPS).
– Although users of the CPU have the ability to write to $r7 using other instructions, doing so would disrupt function call/return operations.
– The Register $r6 be used as the stack pointer, while $r0 should always hold the constant value of 0.
Regarding the implementation, it is important to note that the read ports of the register file must use Tri-state Buffers and a Decoder instead of a large Mux.
3. ResetInput
The CPU features a sole input referred to as “reset”, which must be named exactly as such. This input allows for the computer’s state to be reset by performing the following actions:
1. Asynchronouslyresettheprogramcounter(PC)to0.
2. AsynchronouslycleartheTTYdisplay.
3. Asynchronouslyclearthekeyboardinputbuffer.
4. Asynchronouslyresetallregistersintheregisterfiletozero.
Please note that the Reset input will not have any impact on the instruction or data memory. This can be accomplished by linking the reset input to the “clear” or “reset” input pins on the D Flipflops and IO devices that are utilized.
4. ClockingtheCPU
Please not that there should only be five clocked items in your design (PC register, register file, data memory, keyboard and TTY).
CLOCK REQUIREMENT:
• Clock the register file, and TTY on the rising edge of the clock. •
Clock the PC register, data memory, and keyboard on the falling edge.
5. MemoryLayout
The assembler we provide follows the conventions for memory allocation as shown in Figure 1. This is referred to as a “Harvard architecture”, which simply means that separate memory spaces are designated for instructions and data. This aligns with the distinct “instruction fetch” and “load word” functions present in our CPU’s data path. Furthermore, we reserve the top half of each memory region for the kernel, even though no kernel or operating system exists for this architecture. Therefore, user programs can have addresses ranging from 0x0000 to 0x7FFF in instruction memory, while the first 8 Kwords (0x2000 words) in data memory are reserved for static data, with the heap starting at address 0x2000 and expanding upward, and the stack starting at address 0x7FFF and expanding downward. Please note that this architecture is WORD-addressed, not BYTE-addressed, meaning that each address corresponds to a complete 16-bit word.
To implement this, you can use a Logisim ROM memory block for instruction memory and a Logisim RAM block for data memory. You may edit the values in these memory blocks manually, or alternatively, right-click (or control-click for Mac users) to access a popup menu that enables you to load an image file. These image files will be created by the assembler discussed later in this document.
Logisim Restrictions: On this assignment, you may only use the following Logisim elements:
1. Anythingfromthe“Wiring”folder
2. Anythingfromthe“Gates”folder
3. Anythingfromthe“Plexers”folder
4. Fromthe“Memory”folder:“DFlip-Flop”,“RAM”,and“ROM”
**Note: when deploying RAM in Logisim Evolution, you’ll need to couple it with a “memory_latch” circuit we are providing you; see the section “Using RAM in Logisim Evolution” below.
5. Fromthe“Input/Output”folder:“Keyboard”,“TTY”,and“Button”. 6. The“Text”tool
Programming Help
Using RAM in Logisim Evolution
**We will provide you a folder with the automated tester (hwtest.py and associated files), the example programs used by the tester (programs/), and the assembler+simulator (asmsim/).
1. LaydownyourRAMinyourmaincircuitandconfigureasfollows:
a. Addressanddatawidthshouldbe16-bit.
b. b.Triggeringshouldbeonhigh-levelinsteadofonanedge.
c. c. Databus implementation should be separate read/write ports.
2. Findthememorylatch.circprovidedviaFolder,andmergethecontentsyour cpu.circ: With your CPU open, use the “File | Merge” option in Logisim Evolution to merge in the memorylatch.circ file. This will add a memory_latch subcircuit.
3. Placeamemory_latchinstancebeforeyourRAMinyourmaincircuit.Insteadof sending your data and address directly to your RAM, you should send them to the memory_latch instance (along with a NOT(clock) signal and a write_enable signal) and this latch will generate an “address_latched”, “data_in_latched”, write-enable latched (“WE_latched”) and output-enable latched (“OE_latched”) which you should then send to the RAM that is level triggered. You could change the representation to hook into your RAM compactly, as shown above.
What you don’t need to worry about
– Stack management – the stack is a convention maintained by programmers writing code for your CPU; you don’t have to do anything to make it exist. This means that even though we’ve said that $r6 is the stack pointer, you as the CPU designer don’t have to do anything special to allow or enforce this.
– Heap management – same as the stack; it’s maintained by the programmers so you don’t have to do anything to make it exist. This means that even though the heap is supposed to start at 0x2000, you as the CPU designer don’t have to do anything special to allow or enforce this.
– The kernel – there’s no OS kernel for your CPU, and user programs running on your CPU will have direct access to the I/O devices (keyboard+TTY), so you don’t need to worry about inventing syscalls, protected instructions, exceptions, etc.
– The “Harvard architecture” (separate instruction and data memory spaces) will happen naturally if you simply design the CPU in the way we described
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