Design Project – Prime Finder
Section 1: Introduction
Prime Finder
This section provides a brief introduction and overview of the design project.
Your Mission
Design a system, called “Prime_Finder” that can determine whether a 4-bit binary number is prime.
Motivation
Prime numbers have interesting a useful properties. For example, prime numbers are at the heart of modern cryptograpphic techniques for encrypting information so that it can be transmitted securely over a network. Specifically, public key cryptography and the RSA algorithm both and rely on the use of prime numbers. You will learn more about encription techniques in the 4th year module EBU7140 (Security and Authentication).
Total Available Marks
This lab. assessment is worth 8 marks in total. Note that 1 mark is equivalent to 1% of the module mark. So, one could obtain up to 8% of the module mark by completing this assessment. Students who complete phase 1 only will receive between 0 and 4 marks. Students wishing to obtain a higher mark must also complete phase 2. Those phases are described below.
Overview of Phase 1 and Phase 2
Phase 1 (Mandatory – worth 0 to 4 marks): Follow the guidance in this lab. brief to develop a fundamental system that can detect whether a four bit binary number is prime. You will need to prepare working code for the system. You wll also need to download that code onto the DE10-Lite development board and demonstrate that it functions as required.
Phase 2 (Optional – worth 4 to 8 marks): Do something innovative and unique to improve the fundamental design, developed in phase 1. There are a wide range of different options available to you. However, your work, in phase 2, must focus on improving systems ability or performance.
Section 2: Detailed Description of Phase 1
This section provides detailed specifications for the system to be designed in phase 1.
Structure of the Design
Table 1 outlines the subsystems (or blocks) that must form part of your overall system. You will lose marks if these blocks are not included or if the blocks do not follow the specifications given. You should not employ any additional blocks of code beyond the ones listed in Table 1.
Table 1. Subsystems (or blocks) that must form part of your overall system.
No. Block Name Description Child Parent No.
A circuit that ANDs two single bits together and produces a single bit output.
Must be constructed from an AND logic gate.
Full_adder
A circuit that adds two single bit numbers, and a carry in, together. The output is a single bit binary number and a carry out.
Must be constructed from AND, OR, and XOR logic gates in the way that we saw in the lectures (block 2, lecture: “EBU6335-24_08-Adders”).
Design Project – Prime Finder
Multiplier_4bit
A circuit that multiplies two 4-bit binary numbers together to produce an 8-bit binary output.
Must be constructed from full adders as well as AND gates in the way that we saw in the lectures (block 4, lecture: “EBU6335-24_20-Arithmetic”, slide 24).
You must employ the modular approach that we saw in the lectures (block 1, lecture: “EBU6335- 24_04-VHDL_CircuitModel”).
Parent of Child 1 and Child 2
RipSub_4bit
A ripple adder configured to subtract one 4-bit binary number from another. The circuit should produce a 4-bit binary output along with a carry out.
Must be constructed from AND, OR, XOR, and NOT logic gates in the way that we saw in the lectures (block 2, lecture: “EBU6335-24_08- Adders”).
LongDivision_4bit
A circuit to divide one 4-bit binary number by another. The circuit should generate a 4-bit binary quotient and a 4-bit binary remainder.
The code should implement the principles of long division. The main part of the code should consist of a process statement incorporating several if statements, or equivalent.
Parent of Child 3 and Child 4
Prime_Finder
A circuit that inspects the quotient and remainder, generated by “LongDivision_4bit” in order to determine whether the Dividend is a prime number.
Parent of Child 5
Only “LongDivision_4bit” and “Prime_Finder” may use the library “IEEE.std_logic_unsigned.all”. This will enable you to make use of the + and – operators in those blocks. However, the + and – operators may only be used to increment and decrement counters. You must also use clock and load signals in the “LongDivision_4bit” and “Prime_Finder” blocks.
Table 1 lists 6 blocks of code. Most groups have between 4 and 6 people. Please divide the work between the group members evenly. When considering the division of work please consider the degree of difficulty involved in generating each block. For example, block 1 is straightforward and the person who develops it can also develop another block. One person should be responsible for developing each of the main blocks (i.e. blocks 3 to 6). You should work together to ensure that the blocks are compatible with one another and that they work successfully together to yield the correct overall system operation.
Design Project – Prime Finder
Top-Level Inputs and Outputs Required
Fig. 1 shows a block diagram for the top-level design entity within “Prime_Finder”. By inspecting Fig. 1 you will be able to determine the inputs and outputs that are required.
Fig. 1. Block diagram for the top-level design entity within “Prime_Finder”.
Programming the DE10-Lite FPGA Development Board
Initially you will be required to demonstrate that your code works by using a testbench file in the ModelSim software. Later you will need to programme the DE10-Lite FPGA development board and demonstrate that your design works on the board. The inputs and outputs should be allocated to hardware on the board, as shown in Table 2.
Table 2. Correspondence between signals and resources on the DE10-Lite FPGA development board.
Signal Name
Dividend Divisor Load Dividend_out Divisor_out Is_Prime
Resource on the Board
SW0 to SW3 SW4 to SW7 SW8 HEX0 and HEX1 HEX4 and HEX5 LED0
Fig. 2 shows the input and output devices associated with the DE10-Lite FPGA development board.
Fig. 2. Input and output devices associated with the DE10-Lite FPGA development board.
You must test each block of code separately and provide suitable evidence to show that it works. The evidence will take the form of a short video in which you must clearly show your code along with evidence, from the waveforms generated in ModelSim. Also, you must demonstrate that the system, as a whole, works on the DE10-Lite FPGA development board. See Section 4, for more information.
Computer Science Tutoring
Design Project – Prime Finder
File Structure and Naming
Table 1 outlines the hierarchy of files required for this project. You must name your top level design file Prime_Finder_GroupX where X is your group number in decemal format (i.e. 10). All of the sub-files within your project should incorporate the extension GroupX where X is your group number in decemal format (i.e. 10).
Restrictions
The following restrictions apply to your design files (with the exception of testbenches) for the design project:
1. You must design each of the functions, decribed in Table 1, in a way that reflects the hardware that would be needed to implement those functions. For example, the addition must be performed using full adders and you must perform long hand multiplication and division. This was explained in detail in Table 1.
2. Within blocks 1 to 4 you are only allowed to use the libraries “IEEE.std_logic_1164.all” (not “std_logic_arith”, “std_logic_unsigned”, etc.).
3. You may chose to use the libraries “std_logic_arith” and “std_logic_unsigned” in blocks 5 and 6, where they can be used to increment and decrement counters only.
4. You may use any intermediate signals, logic operators, relational operators.
5. You may use any signal assignment statements, conditional signal assignment
statements (when-else, with-select).
6. You may use VHDL processes in your circuit models and testbenches.
Section 3: Detailed Description of Phase 2
This section provides further details on what you need to do, if you wish to complete phase 2.
For phase 2 you must do something innovative and unique to improve the basic design. There are a wide range of different options available to you. However, your work, in phase 2, must focus on improving systems ability or performance in detecting prime numbers.
Examples of things that you could try are given below:
◦ Extend the number of bits beyond 4, so that the system can test larger numbers.
◦ Increase the speed at which the system can detect a prime number.
◦ Reduce the number of resources used by the design.
Let us consider that you chose to make improvements to the design (such as increasing the computational speed). Be aware that the benefit of your improvement can only be determined through comparison with the original design. To this end you must compare the performance of your phase 1 design with that of you phase 2 design. You will need to clearly explain and provide evidence to prove, the performance improvement that you claim to have acheived. Your assessors will not have time to search for this evidence for themselves so you need to provide it. This is your responsibility.
Section 4: Submission Instructions
This section explains what you need to submit and how to go about doing that. Further details and information will be provided nearer to the submission deadline.
Submission 1 – Demonstration Video
Prepare a video demonstrate that your design works correctly. The total duration of the video should be up to a maximum of 8 minutes. You must communicate in English throughout that video. The video should contain the following parts:
1) A self-introduction during which you give your name and QMUL student ID. Please show your face in this part (~30 secs).
2) Validate each of the 4 main blocks (i.e. blocks 3 to 6), listed in Table 1, separately in
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Design Project – Prime Finder
ModelSim. You will need to generate suitable testbench files, for this purpose. Try to
explain the testbench files and the simulation results (~2 min).
3) DownloadthecodetotheDE10-LiteFPGAdevelopmentboardandverifycorrectoperation
of the overall system. Again, try to explain your test cases and the results (~1 min 30 secs). 4) During the discussion involved in parts 2) and 3) try to demonstrate your knowledge of
circuit design, VHDL modelling and usage of the software tools (~4 mins).
Submission 2 – Zip folder containing the VHDL code
A zip folder containing the VHDL code for the 6 blocks, listed in Table 1. The zip folder should also contain the project file and the testbench file. The folder of files must be complete and capable of being opened and ran directly in Quatus Prime. Please check that this is the case before uploading it to QMPlus. If we cannot open and run your file then we will not be able to examine it. This is your responsibility.
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