Computer Organization
Final Project – Simple Processor
Design Description
A processor executes operations specified in the form of instructions. In this project, a string of instructions will be given. Your job is to decode these instructions and execute.
⮚ The following is the basic required instruction format: (similar to MIPS)
Type R-type I-type
opcode (6)
opcode (6)
rs (5)
rs (5)
Fields (32 bits)
rt (5) rd (5) shamt (5) funct (6) rt (5) immediate (16)
Register s(rs), Register t(rt) and Register d(rd) represent the address of registers. Since the instruction takes 5 bits to store the address, it means we have 32 registers, from r[0] to r[31]. Each register reserve 32 bits to store data, e.g. rs = 5’b00000 means one of operands is “r[0]”. rt = 5’b00101 means one of operands is “r[5]”, and so on. The register file [31:0] r[0:31] have been declared by TA in SP.v. DO NOT edit the name of register file, or TA’s pattern would catch wrong results.
⮚ The following is the required instruction set of this design: Type Function Description
opcode funct 0x00 0x00 0x00 0x01 0x00 0x02 0x00 0x03
0x00 0x05 0x00 0x06
PC ← PC + 4 + SE({imm, 00})
bne if(R[$rs] != R[$rt]) 0x08
PC ← PC + 4 + SE({imm, 00})
lui R[$rt] ← {imm, 0x0000} 0x09
and R[$rd] ← R[$rs] & R[$rt] or R[$rd] ← R[$rs] | R[$rt] add R[$rd] ← R[$rs] + R[$rt] sub R[$rd] ← R[$rs] – R[$rt]
slt
if(R[$rs] < R[$rt])
R[$rd] ← 1
else
R[$rd] ← 0
0x00
0x04
R-type
I-type
sll R[$rd] ← R[$rs] << shamt
nor R[$rd] ← ~(R[$rs] | R[$rt])
andi R[$rt] ← R[$rs] & ZE(imm) 0x01 ori R[$rt] ← R[$rs] | ZE(imm) 0x02 addi R[$rt] ← R[$rs] + SE(imm) 0x03 subi R[$rt] ← R[$rs] – SE(imm) 0x04 lw R[$rt] ← Mem(R[$rs] + SE(imm)) 0x05 sw Mem(R[$rs] + SE(imm)) ← R[$rt] 0x06 beq if(R[$rs] == R[$rt]) 0x07
In the above table, SE or ZE mean doing sign extension or zero extension on the number. There will be a 4096 * 32 data memory in this project. You can access this memory according to the instruction.
The pattern also be used as instruction memory in this project. You should access pattern with inst_addr (PC) to get next instruction. Be careful of the 4 bytes offset.
Design Inputs and Outputs
■ The following are the definitions of input
signals. Description
Positive edge trigger clock.
Asynchronous active-low reset.
High when inst is valid.
Instruction given be pattern.
Data output from memory according
Input Signal clk
rst_n in_valid inst
Connection PATTERN
PATTERN PATTERN PATTERN
Bit Width 1
1
1
32
mem_dout
■ The following are the definitions of output signals.
MEM
to mem_addr. Description
Pattern will give next Instruction according to inst_addr if out_valid is high.
Next instruction address. (PC)
Data memory address input. Data memory data input
32
Output Signal
out_valid inst_addr
mem_addr mem_din
Connection
PATTERN PATTERN
MEM MEM
Bit Width
1 32
12 32
mem_wen
MEM
1
When WEN is high, you can load data from memory.
When WEN is low, you can write data into memory.
Specification
1. Top module name: SP (Design file name: SP.v)
2. It is asynchronous and active-low reset. If you use synchronous reset in your
design, you may fail to reset signals.
3. The reset signal (rst_n) would be given only once at the beginning of simulation.
4. inst_addr, out_valid and register file r should be reset after the reset signal is
asserted.
5. The out_valid is limited to be high for only 1 cycle in non pipeline design.
6. out_valid should not be raised when in_valid is high for non pipeline design.
7. The out_valid should be raised within 10 cycles after in_valid raised.
8. Next instruction will be given in the next cycle after out_valid is raised.
9. Pattern will check the register file r result and inst_addr for each instruction at
clock negative edge when out_valid is high.
10. Pattern will check the final result of mem.v.
11. Released and demo pattern will not cause overflow.
Additional specification for pipelined design
12. Use the same instruction.txt and mem.txt file as non-pipeline design.
13. Use TESTBED.v, PATTERN.v to test non-pipeline design.
14. Use TESTBED_p.v, PATTERN_p.v to test pipeline design.
15. No need to consider branch prediction. The correct inst_addr should be given by
design after instructions fetched.
16. No need to consider data hazards. data dependency or load-use will be separated
by at least two instructions to avoid data hazards in pattern.
17. Once out_valid raised, it should be kept high until simulation end.
18. Pattern will check the sequence inst_addr.
Block Diagram
Example Waveform
Non-pipeline
Pipeline
Grading Policy
1. Pipelined design : 10%
2. Function validity (released pattern): 60%
3. Function validity (demo pattern): 40%
⮚ Only 20% for 2nd demo. Note
● Please upload “SP_studentID.v” or “SP_studentID_pipeline.v” (for pipelined deisgn) on New e3.
● You can submit both pipeline and non pipeline design, TA will choose the higher grade you submitted.
● 1st demo Due Date: 23:59, Jan 15, 2023.
(If you have a late submission by 1 to 7 days, you will only get 80% of the score. We DO NOT accept any late submission after 7 days after the deadline.)
● If the uploaded file violates the naming rule, you will get 5 deduct points on this project.