COMP3222 9222 Digital Circuits & Systems

Computer Architecture 体系结构代写, Computer Network 计算机网络代写 / CS代考, Verilog 代写, VHDL 代写

COMP3222/9222 Digital Circuits & Systems
21T3 L01 – Introduction
Course website: www.cse.unsw.edu.au/~cs3222
Oliver Diessel
O: K17-501B
E: P: 9385 7384

What you will learn in this class
• Introduction to the design of digital logic circuits
– Boolean algebra, logic minimization, combinational logic components, sequential circuits, simple systems
• Principles of creating digital circuit designs
– using VHDL hardware description language
– simulation techniques to verify the correct working of designs
– logic compilers to synthesize hardware
– implementing and testing designs using programmable hardware
20T3 COMP3222/9222 Introduction L01/S2

What is logic design?
• What is design?
– given a specification of a problem, come up with a way of solving it choosing appropriately from a collection of available tools, techniques and components
– while meeting certain performance criteria for size, cost, power, beauty, elegance, etc.
• What is logic design?
– determining the collection of digital logic components and the interconnections between them to perform a specified data gathering, processing, storage, control and/or communication function
– which logic components to choose? – there are many implementation technologies, with differing costs/benefits
– the design may need to be optimized and/or transformed to meet design constraints
20T3 COMP3222/9222 Introduction L01/S3

Applications of logic design
• Computer hardware & systems
– design of processors, CPUs, systems, accelerators, custom chips, buses, interfaces, memories, peripherals
• Communications & networks
– I/O devices, phones, switches, routers, base stations, satellites
• Embedded systems
– consumer electronics, appliances, entertainment devices, IoT, medical devices, security, transport, robotics, mining, agriculture and manufacturing equipment
• Scientific instruments & equipment
– simulation, testing, sensing, logging, reporting, analyzing
• Challenge:
– Which human activities (a) don’t yet, and (b) won’t ever involve digital technology?
20T3 COMP3222/9222 Introduction L01/S4

Why study logic design?
• Obvious reasons
– fundamental abstraction for implementing all digital devices
– to study the digital design process
– this course is part of the CompEng requirements
• Other important reasons
– it’s an important counterpart to software design
high performance
– it’s essential to furthering our understanding of the efficient implementation of computation
– the inherent parallelism in hardware provides exposure to real parallelism on a large, fine-grained scale
20T3 COMP3222/9222 Introduction L01/S5

COMP3222/9222 details
21T3 COMP3222/9222 Introduction L01/S6
• Lectures,Weeks1–51,07-10
– RMeocno1rd6i-n1g8sCaovlaoimlabloeTohnBwebsiteforasynchronousviewing
• I assume you have viewed the relevant recording before the synchronous – Wed14-16AinsworthG02
meetings – see the Lecture schedule on the course website
– Synchronousmeetingstoreviewmainpoints,discussquestionsandwork
• Labs, Weeks 1 – 10
through exercises: Mon 14–16 & Wed 16–18
– 2hrLabs:Tue12-14,Wed16-18,Wed18-20,Thu10-12,Thu12-14 in K17 Lyre lab
• Labs, Weeks 1 – 10
– Pickuptake-homelabkitduringfirstlab(thisweek)
– Labexercisesandresourcesavailableonwebsite
– 3hrofficialonlinedrop-insessionwhereyoucanobtainhelpandask
• Tutes, Weeks 2 – 10
questions of demostrators: Wed 12–15
– 1hrTutes:Tue14-15,Tue15-16QuadG045,
– 2hroptionalonlinedrop-insessions:Tue14–16,Thu12–14
Thu 14-15, Thu 15-16 Quad G031
– SubmissionsdueroughlyeachweekonMondaysat23:59

COMP3222/9222 assessment
• Assessment:
– 7labexs(duetheweekaftertheyarescheduled):40%total
– 4fortnightlyquizzesontheoryinWeeks3,5,7&9:15%total
– 1hrFinalTheoryTest:15%
– 2hrFinalPracticalTest:30%(needtoscore>40%inPracExam to pass course)
• Supplementaries
– Onlyoneeligibilitycriterion:
1. Need to score >45% overall and >36% in Practical Test ⇒ final score = 50% if supp passed
2. Certified medical excuse ⇒ final score calculated as if sitting normal exam
– Note: there is no supp for missing the lab submission deadlines or
21T3 COMP3222/9222 Introduction L01/S7

COMP3222/9222 text
• Brown & Vranesic, Fundamentals of Digital Logic with VHDL Design, 3ed, McGraw-Hill
– out of print, so not available at bookshop
– available for short loan from the Library
– exercises drawn from text
– extracts of Ch 1 & 2 provided on course website
– text is designed to be used with the FPGA board you will be using
• containstutorialsonloading&usingtheCADtools
• providesadetailedreferenceonVHDL
• willbeaninvaluableaidinthefollow-oncomputerarchitecture& design project courses
21T3 COMP3222/9222 Introduction L01/S8

Acknowledgement
• Most of the slides in this course are modified from the current text (Brown & Vranesic), or from Katz, Contemporary Logic Design, 2ed, Pearson
• The material provided by these authors is gratefully acknowledged
20T3 COMP3222/9222 Introduction L01/S9

Digital circuits
• The study of digital logic circuits is primarily motivated by their use in digital computers
• Logic circuits perform operations on digital signals and are usually implemented as electronic circuits in which the signal values are restricted to a few discrete values
– In binary logic circuits, there are only two values, 0 and 1 – Decimal logic circuits would have 10 values
• In contrast, in analog circuits, signals may take on continuous values between maximum and minimum levels
• We will only consider binary digital circuits
– These are dominant because of their simplicity
– The simplest binary element is a switch that has two states
20T3 COMP3222/9222 Introduction L01/S10

A binary switch
open closed
(a) Two states of a switch
(b) Symbol for a switch
• We say the switch is controlled by input variable x, and that the switch is open if x = 0 and closed if x = 1
20T3 COMP3222/9222 Introduction L01/S11

A light controlled by a switch
• The state of the light L is dependent on the state of the switch
• Thelightison,L=1,
• Thelightison,L=
(a) Simple connection to a battery
closed, x = 1, and vice versa
if the switch is closed,
1, if the switch is
x = 1, and vice versa
• Thus L(x) = x
• Thus L(x) = x
(b) An equivalent circuit using a ground connection as the return path
20T3 COMP3222/9222 Introduction L01/S12

Two basic functions
In a series connection, both switches need to be closed for the light to be on
Thus, L(x1, x2) = x1 ∙ x2
In a parallel connection, either one of the switches need to be closed for the light to be on
Thus, L(x1, x2) = x1 + x2
(a) The logical AND function (series connection)
(b) The logical OR function (parallel connection)
20T3 COMP3222/9222 Introduction

A series-parallel connection
L(x1, x2, x3) = ?
Which function determines the output of the light? How many possible states are there for this circuit? How many of these have the light on?
20T3 COMP3222/9222
Introduction L01/S14

Power supply
• Since the switch, when it is closed, short-circuits the potential difference across the light:
L(x) = x, where L = 1 if x = 0 and L = 0 if x = 1
• The complement op, NOT, is expressed in many ways:
x = x’ = !x = ~x = NOT x
20T3 COMP3222/9222 Introduction L01/S15

Truth tables for the AND, OR and NOT operations
20T3 COMP3222/9222 Introduction
AND OR NOT

Basic gate symbols
• Each logic operation can be implemented electronically with transistors, resulting in a circuit element called a logic gate
• Each logic gate has one
or more inputs and one output that is a function
of its inputs x1
• A logic circuit is often x2 described by drawing a circuit diagram, or schematic, consisting of graphical symbols representing the logic gates
(a) AND gates
x1 ∙x2 ∙…∙xn
x1 + x2 + … + xn
(b) OR gates
20T3 COMP3222/9222
(c) NOT gate

The function from L01/S14
f = (x1+x2)∙x3
• A larger circuit is implemented by a network of gates
• Such circuits are called logic networks or logic circuits
• The complexity of a given network (in terms of the gate count & number of gate inputs) has a direct impact on its cost
• In order to reduce manufactured cost, we seek ways to implement logic circuits as inexpensively as possible
– Smaller (simpler) circuits are also faster and less susceptible to failure
20T3 COMP3222/9222 Introduction L01/S18

Analyzing a logic network
xx ABf(x,x) 12 12
0®0®1®1 0®1®0®1
1®1®0®0 0®0®0®1
1®1®0®1 f = A + B = x1 +x1 ∙x2
(b) Truth table
(a) Network that implements
0®0®1®1 1®1®0®0 0®1®0®1
(d) Network that implements
(c) Timing diagram/waveform
1®1®0®1 g = x1 + x2
Note that g implements the same function as f but at a lower cost!
20T3 COMP3222/9222
Introduction

Axioms and theorems of Boolean algebra
The theory underlying the simplification of logic expressions and their cir- cuit realization is founded on the axioms and theorems of Boolean algebra
• identity Dual 1. X+0=X
• idempotency:
• involution:
4. (X’)’ = X
• complementarity: 5. X+X’=1
• commutativity:
6. X+Y=Y+X
• associativity:
7. (X+Y)+Z=X+(Y+Z)
2D. X•0=0 3D. X•X=X
5D. X•X’=0
X is a Boolean variable with two possible values: true = 1 or false = 0
7D. (X•Y)•Z=X•(Y•Z)
20T3 COMP3222/9222 Introduction L01/S20
6D. X•Y=Y•X

Axioms and theorems of Boolean algebra
• distributivity:
8. X•(Y+Z)=(X•Y)+(X•Z) 8D. X+(Y•Z)=
• uniting:
9. X•Y+X•Y’=X
• absorption: 10.X+X•Y=X
11. (X + Y’) • Y = X • Y
• factoring:
12. (X + Y) • (X’ + Z) = X • Z + X’ • Y
• consensus:
13. X • Y + X’ • Z + Y • Z = X • Y + X’ • Z
(X+Y)•(X+Z)
9D. (X+Y)•(X+Y’)=X
10D. X•(X+Y)=X 11D. (X • Y’) + Y = X + Y
12D. X • Y + X’ • Z =
(X + Z) • (X’ + Y)
13D. (X + Y) • (X’ + Z) • (Y + Z) = (X + Y) • (X’ + Z)
20T3 COMP3222/9222
Introduction

Axioms and theorems of Boolean algebra
• de Morgan’s:
14. (X + Y + …)’ = X’ • Y’ • … 14D. (X • Y • …)’ = X’ + Y’ + …
• generalized de Morgan’s:
15. f(X1,X2,…,Xn,0,1,+,•) = f(X1,X2,…,Xn,1,0,•,+)
• establishes relationship between • and +
f=x2 +x1x3 Þ f=x2 +x1x3
= x2 • x1x3 =x2 •(x1+x3) =x2 •(x1+x3)
20T3 COMP3222/9222 Introduction L01/S22

Axioms and theorems of Boolean algebra
– a dual of a Boolean expression is derived by replacing • by +, + by •, 0 by 1, and 1 by 0, and leaving variables unchanged
– any theorem that can be proven is thus also proven for its dual!
– is a “meta-theorem” (a theorem about theorems) • duality:
16. X + Y + … Û X • Y • …
• generalized duality:
17. f (X1,X2,…,Xn,0,1,+,•) Û f(X1,X2,…,Xn,1,0,•,+)
• Differs from deMorgan’s Law
– Duality is a statement about theorems
– Duality is not a way of manipulating (re-writing) expressions
20T3 COMP3222/9222 Introduction L01/S23

Axioms and theorems of Boolean algebra
• Proofs of the axioms and theorems of Boolean algebra can be established in various ways
– For example, the absorption theorem (X + X • Y = X) may be proven deductively, exhaustively or using set theory
LHS = X • 1 + X • Y by identity LHS = X • (1 + Y) by distributivity LHS = X • 1 by null
LHS = X by identity
X Y X•Y X+X•Y 0000 0100 1001 1111
20T3 COMP3222/9222
Introduction L01/S24
Using set theory, the surrounding box represents the universe, logical AND
is given by the intersection of sets, and logical OR is given by the union of sets

Precedence of operations
• In the absence of parentheses, operations in a logic expression must be performed in the order:
NOT, AND, and then OR
x1∙x2 + x1∙x2 has the same effect as (x1∙x2) + ((x1)∙(x2))
• Also, to simplify the appearance of logic expressions it is customary to omit the ∙ operator when there is no ambiguity
– The preceding expression can therefore be written as
x1 x2 + x1 x2
20T3 COMP3222/9222 Introduction L01/S25

Synthesizing digital logic circuits using AND, OR and NOT gates
x1 x2 f(x1, x2) 001 011 100 111
(a) Function to be realized
f(x1,x2) = x1x2 + x1x2 + x1x2
(b) Canonical sum-of-products realization
x f(x1,x2) = x1x2 + x1x2 + x1x2 + x1x2 idempotency 1
f(x1,x2) = x1(x2 + x2) + (x1 + x1)x2 f(x1,x2) = x1∙1 + 1∙x2
f(x1,x2) = x1 + x2
distributivity x2 complementarity identity
(c) Minimal-cost realization
20T3 COMP3222/9222
Introduction

Evaluating circuit cost
• The primary contributor to circuit cost is the number of transistors used
• #(Transistors used) ≈ circuit (chip) area
• Circuits with fewer gates and gates with fewer wires
(inputs) require fewer transistors ⇒ less chip area
– Important: the lowest level of abstraction we will use to design digital circuits is the GATE LEVEL (we will only look at how gates are implemented using transistors at the end of the course)
• Unless stated otherwise, we will use the sum of the number of gates and the total number of gate inputs within a circuit as a measure of circuit cost
– With this metric, circuit (b) on the previous slide has a cost of 17, whereas circuit (c) has a cost of 5
20T3 COMP3222/9222 Introduction L01/S27

Synthesis technique for logic circuits
1. Addaproduct(AND)termforeachrowinthetruth table with function value f = 1
2. Formthesum(OR)ofthesetermstoproducethe function f
3. SimplifytheexpressionusingBooleanalgebraic manipulation
4. Drawthecircuit,complementinginputswhere necessary, using AND gates for the product terms and ORing these together
20T3 COMP3222/9222 Introduction L01/S28

The result of ANDing variables together
• Three-variable minterms
Note that minterms are numbered according to which variables appear in uncomplemented form
For a function of
variables, a product
in which each of the
variables,
exactly once is called a
– The variables may appear in a minterm either in uncomplemented or complemented form
– For a given row of the truth table, the minterm is formed by including xi if
xi = 1 and by including xi if xi = 0
– Note that mi=1 in row i of the truth table and mi=0 in all other rows 20T3 COMP3222/9222 Introduction L01/S29

Sum-of-Products form
• A function f can be represented by an expression that is written as a sum of minterms, where each minterm is ANDed with the value of f for the corresponding valua- tion of input variables
• For example, for the function of slide L01/S26,
f(x1, x2) = m0∙1 + m1∙1 + m2∙0 + m3∙1
=m0 +m1 +m3 =Σ(m0,m1,m3)
=x1x2 +x1x2 +x1x2 =Σm(0,1,3)
x1 x2 f(x1, x2) 0 0 1 011 100 111
• A logic expression consisting of product (AND) terms that are summed (ORed) is said to be in the sum-of-products (SOP) form.
• If each product term is a minterm, then the expression is called a canonical sum-of-products for the function f
– Every Boolean fn has just ONE canonical SOP representation 20T3 COMP3222/9222 Introduction L01/S30

Example 2.3
• Consider the function f(x1, x2, x3) = Σm(2, 3, 4, 6, 7)
• The canonical SOP expression is given using minterms
f(x1,x2,x3)=m2 +m3 +m4 +m6 +m7
= x1x2x3 + x1x2x3 + x1x2x3 + x1x2x3 + x1x2x3
• The expression can be simplified using algebraic manipulation:
f = x1x2(x3 + x3) + x1(x2 + x2)x3 + x1x2(x3 + x3)
= x1x2 + x1x3 + x1x2 = (x1 + x1)x2 + x1x3 = x2 + x1x3
…SOP form
…Not in SOP form …SOP form
20T3 COMP3222/9222
Introduction
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• The principle of duality suggests that if it is possible to synthesize a function f by considering the rows in the truth table for which f = 1, then it should be possible to synthesize f by considering the rows for which f = 0
• This alternative approach uses the complements of minterms, which are called maxterms
20T3 COMP3222/9222 Introduction L01/S32

1 0 0 0 0 0 0 0
0 1 1 1 1 1 1 1
minterm m0 maxterm M0
Three-variable minterms and maxterms
M0 =m0 =x1x2x3 =x1 +x2 +x3
(derived using DeMorgan)
Observe the value of the example and for each valuation of the variables x1, x2, and x3
Note that maxterm Mi=0 in row i of the truth table and Mi=1 for all other rows
20T3 COMP3222/9222 Introduction L01/S33

Product-of-Sums form
• If a given function f is specified by a truth table, then its complement f can be represented by a sum of minterms for which f = 1, which are the rows of f where f = 0.
• For example, for the L01/S26 function, f(x1,x2) = Σm(0,1,3), f(x1,x2) = m2 = x1x2
• If we complement this expression using DeMorgan’s theorem,theresultisf=f=x1x2 =x1 +x2 =M2
• Thekeypointisthatf=m2 =M2=Π(M2)=ΠM(2)
• A logic expression consisting of sum (OR) terms that are factors of a logical product (AND) is said to be of the product-of-sums (POS) form
• If each sum term is a maxterm, then the expression is
called a canonical product-of-sums for the given function 20T3 COMP3222/9222 Introduction L01/S34

Example 2.4
• Consider again the function of Example 2.3. Instead of using the minterms, we can specify this function as a product of maxterms for which f = 0, namely,
f(x1, x2, x3) = ΠM(0, 1, 5)
• Then the canonical POS expression is given by:
f(x1, x2, x3) = M0∙M1∙M5
=(x1 +x2 +x3)(x1 +x2 +x3)(x1 +x2 +x3)
• A simplified POS expression can then be derived as:
f=((x1+x2)+x3)((x1 +x2)+x3)(x1 +(x2 +x3))(x1 +(x2 +x3))
= ((x1 + x2) + x3x3)(x1x1 + (x2 + x3)) What’s the cost of
f(x1, x2, x3) = Σm(2, 3, 4, 6, 7)
= (x1 + x2)(x2 + x3) … by the uniting theorem
this expression?
• And note that use of the distributive property leads to:
f = x2 + x1x3 Is this expression in SOP or POS form? What’s its cost? 20T3 COMP3222/9222 Introduction L01/S35

Exercise for you to do
1. DerivecanonicalSOPandPOSexpressionsforthe three-valued function below.
2. Minimizeeachexpressionandsketchtheresulting circuits.
3. Comparethecostsofalldesigns
Row Number
f(x1, x2, x3)
Introduction

Summary so far
1. Logicdesignisconcernedwithfindingthecheapest implementation of combinational (a.k.a. combinatorial) logic functions
– Circuit cost is measured by summing the number of gates and the total number of gate inputs
2. ThelawsofBooleanalgebracanbeusedtominimize the cost of a combinational logic function
– Typically, these are applied one at a time with the objective of eliminating one or more variables from a term or whole terms from the function
3. Therearetwocanonicalrepresentationsof combinational logic functions:
– Canonical sum-of-products represents a function as a sum (OR) of minterms
– Canonical product-of-sums represents a function as a product (AND) of maxterms
20T3 COMP3222/9222 Introduction L01/S37

Computer Aided Design
A typical CAD flow for logic design
Design conception
DESIGN ENTRY
Schematic capture
Hardware description language
Functional simulation
Design correct? Yes
Hardware Description Language
• HDL is similar to a computer programming language except that it is used to describe hardware; NOT to be executed on a processor
– Similar to a markup language
• We focus on one of two IEEE standard languages that are supported by virtually all vendors that provide digital design technology
Physical design
Timing simulation
20T3 COMP3222/9222
Introduction
Timing requirements met?
Chip configuration
We study VHDL (Very High Speed Integrated Circuit HDL)
The other is Verilog

Use of a graphical tool to provide a logic circuit diagram
• In comparison to schematic capture, use of a hardware description language, such as VHDL, to capture a design’s intent offers a number of advantages
– VHDL source code is plain text, which means it can easily be edited, copied and searched; the designer can also easily include documentation explaining how the design works
– Being a standard language, VHDL provides design portability – a design specified in VHDL can be implemented in different types of chips and with CAD tools from different vendors
– Portability is useful because digital circuit technology changes rapidly – by using a standard language, the designer can focus on the functionality of the circuit without being overly concerned with the details of the implementation technology
– Together with its wide use, these features encourage code sharing and reuse, which aids productivity
20T3 COMP3222/9222 Introduction L01/S39

A little VHDL history
• Developed in the 1980s, when integrated circuit technology was rapidly advancing, as a standard means of documenting complex digital circuits
• Became IEEE standard 1076 in 1987, and was revised in 1993 as IEEE 1164. Updates occurred in 2000 and 2002, as well as most recently, in 2008.
• Originally conceived for documenting circuits, and for modelling circuit behaviour, which allowed it to be used as input to programs for simulating circuit operation
• More recently, it has become popular to use it as a design entry method for CAD tools that synthesize hardware implementations
• VHDL is quite complex; we will restrict ourselves to the study of that subset of the language used for synthesis
20T3 COMP3222/9222 Introduction L01/S40

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A simple logic fn and its VHDL entity declaration
• A VHDL entity declaration expresses what the design unit “looks like” to the outside world, i.e., describes its interface
The “mode” of a signal indicates its direction
: IN BIT ; :OUT BIT);
Signals of type BIT can assume values 0 and 1
ENTITY example1 IS PORT ( x1, x2, x3
f END example1 ;
Valid identifiers start with a letter, and comprise alpha-numeric and
underscore characters
20T3 COMP3222/9222 Introduction L01/S41

A simple logic fn and its VHDL architecture
The architecture of a VHDL design unit describes what the design “looks like” on the inside i.e. what its
behaviour and/or structure is x1
Here, the functionality of the
circuit is expressed using a
simple signal assignment statement
In VHDL, all statements need to be terminated by a semi-colon (;)
Note that in VHDL, the Boolean operators all have the same precedence, hence we must use parentheses to indicate the intended meaning
ARCHITECTURE LogicFunc OF example1 IS BEGIN
f <= (x1 AND x2) OR (NOT x2 AND x3) ; END LogicFunc ; 20T3 COMP3222/9222 Introduction L01/S42 Complete VHDL design entity In our code we’ll use capital letters to represent KEYWORDS in the code; obviously these can’t be used as identifiers Note that VHDL is not case sensitive 20T3 COMP3222/9222 Introduction Four-input example Note that simple signal assignment statements are examples of concurrent assignment statements – they are all “evaluated” at the same time when a signal on the RHS changes value; therefore the order the statements are listed in does not matter 20T3 COMP3222/9222 Introduction L01/S44 浙大学霸代写 加微信 cstutorcs Exercise for you to attempt For the timing diagram depicted below, synthesize the function f(x1, x2, x3) in the simplest SOP form and describe your implementation using VHDL A good rule of thumb for writing clear VHDL: Can you visualize the circuit that should be synthesized from your VHDL code? 20T3 COMP3222/9222 Introduction L01/S45