CE869 Assignment 2: CPU design
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Assignment objectives
Dr Xiaojun Zhai week 20
three weeks from submission deadline electronic only via FASer
This document specifies the second coursework assignment to be submitted by students taking CE869. This assignment is more challenging than the first one and it is meant to provide an opportunity to improve the knowledge of the VHDL language and, more importantly, to design a digital “system”. You will be expected to learn to: a) implement digital system design in VHDL code; b) synthesise and download it to the target hardware; c) test, debug, and verify that the design meets the specifications; d) report about your design.
You are required to design code for your target hardware (a Digilent Basys3 board with a Xilinx Artix 7 FPGA) in order to implement a design that meets the specifications (below). Your design will be varied by testbenches in Vivado simulator. You are required to submit working and correct code and you are strongly encouraged to use a modular coding style (allowing for greater flexibility, maintainability, modularity, and reusability). To show that you master all aspects of the language, your code should prevalently use concurrent statements for combinatorial circuits and sequential code for sequential circuits. Additionally, the use of non-standard packages (e.g. STD_LOGIC_ARITH, STD_LOGIC_UNSIGNED, STD_LOGIC_SIGNED) and BUFFER ports is forbidden, while the use of INOUT ports is accepted only when strictly necessary.
You are supposed to gain familiarity with VHDL coding during the supporting CE869 lectures and through self-study hours, also with the help of the recommended textbooks or any other book about VHDL. You are expected to work on this assignment mostly during lab hours. Your design project should be stored under the Gitlab repository that was assigned to you at the beginning of the course. You are supposed to commit often and describe your progress in the commit messages. In order to promote a learning scheme that values the learning process in addition to the submitted final design, your weekly progress (as traced back by the commit logs) will contribute to your assignment mark.
Design specifications
Your task for this assignment is to implement a 16 bit CPU. To make the assignment feasible within the time frame available for this module, the type of CPU will be fairly simple. In particular, the “program sequencing/control flow instruction” datapath can be modelled after the one on the left of Figure 1, while the “arithmetic/logic instruction” datapath can follow a structure like the one on the right in the same figure. Please notice that when RAE and/or RBE are low, the corresponding output(s) will simply match the input “I” to the register file. The opcodes for the instructions that the CPU is required to implement are given in Table 1. You are also required to implement a decode unit in control unit to interpret the ‘Affects’ and control signals from the output of each instruction.
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Data Input
D 10-bit IR IR
4-bit Increment
PCload Reset
D Clear 4-bit PC
16 locations ×10 bits
Address3-0
Execute Instruction2
Data Output
Control signals
Control signals
Execute Instruction1
Execute Instructionn
Figure 1: The figure shows the “program sequencing/control flow instruction” datapath (left and bottom) and the “arithmetic/logic instruction” datapath (right).
Instruction HALT
MOV Rdd, Rss IN Rdd
NOT Rdd, Rss
LT Rrr, Rqq
INC Rrr, #nnnn
DEC Rrr, #nnnn ADD Rdd, Rrr, Rqq SUB Rdd, Rrr, Rqq AND Rdd, Rrr, Rqq OR Rdd, Rrr, Rqq MOV Rdd, #nnnnnnn
Affects Operation
0000000000 Halt
000100ddss
00100000dd
00110000ss
010000ddss
010100aaaa
011000aaaa
011100aaaa
100000rrqq
1001rrnnnn
1010rrnnnn
1011ddrrqq
1100ddrrqq
1101ddrrqq
1110ddrrqq
1111ddnnnn
Rdd ← Rss Rdd ← Input Output ← Rss
Z Rdd ← NOT Rss Jump to aaaa
Jump to aaaa if Z status flag is unset (i.e. is 0)
Jump to aaaa if Z status flag is set (i.e. is 1) Z SetZto0ifRrr