Transistors, Gate Design and Properties
Brent C. Munsell Computer Organization
• Announcements (~ 5 mins)
• Poll Everywhere (~15 mins)
• Complete ALU Material (~15 mins)
• Transistors
• Voltage and Logic (~35 mins)
• Propagation Delay
Announcements
• Due 9/15 @ 11:55 pm with no late penalty.
• Great job (mean ~86%, mode 100%)!
• Release grades and feedback today or tomorrow (talk to Jesse)
• Release this Friday @ 12 pm
• Due this Sunday @ 11:55 pm
• Post announcement this Thursday.
Transistor
Overview, Design, and Operation
Schematic Diagram
Transistor
Physical Hardware: Along with power (VCC) and ground (GND), four transistors are required to make one two-input NAND gate
Abstraction for humans
Transistor Size?
Intel Video: Really goodJ
Voltage (VCC) and Ground (GND)
Think of a direct current (DC) battery:
• E.g., GND or 0 VDC –
(+) voltage DC
• e.g., VCC = 1.5 VDC or 9 VDC (many
other values) (-) voltage DC
Basic Design
Conceptually, a DC voltage switch!
Vcc = 5 VDC Vout
Vcc = 5 VDC
Vout = Vcc
Vin=50VVDDCC
Vcc = 5 VDC
Vout = GND
Vin=05VVDDCC
switch is open
(Vout pull up to Vcc)
switch is closed
(Vout pull down to GND)
Basic Operation
Let’s work though a simple example
Vcc = 5 VDC Vout
Input (Vin) voltage is ”switching” the output (Vout) voltage
Metal Oxide Semiconductor
(MOS) Transistor
Complementary Pull-up/down Design
n-channel Metal Oxide Semiconductor (nMOS) Transistor
Switch is closed when gate (g) is positive VDC value (e.g., 5 VDC)
Channel is open, electrons can flow from drain to source
n-channel Metal Oxide Semiconductor (nMOS) Transistor
Switch is open when gate (g) is GND (e.g., 0 VDC)
Channel is closed, electrons cannot flow from drain to source
p-channel Metal Oxide Semiconductor (pMOS) Transistor
Switch is open when gate is positive VDC value (e.g., 5 VDC)
Channel is closed, electrons cannot flow from source to drain
p-channel Metal Oxide Semiconductor (pMOS) Transistor
Switch is closed when gate is GND (e.g., 0 VDC).
Channel is open, electrons can flow from source to drain.
NOT Gate MOS Gate Design
Schematic Diagram
Truth Table
Vcc = 5 VDC
pMOS transistor
nMOS transistor
Complementary MOS Design
pMOS transistor AY
nMOS transistor
NAND Gate: MOS Design
pMOS transistor
nMOS transistor
Vcc = 5 VDC
NOR Gate: MOS Design
Vcc = 5 VDC
Relationship between Voltage and Logic
Digital abstraction
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Voltage and Logic
Voltage a continuous value
• Has a defined range of values, e.g., 0 to 5 VDC
• And any VDC value between, e.g., 0.1, 0.11, 1.25, 4.52, etc.
• Hardware understands voltage values
Boolean Logic (or Logic for short) is a discrete value that can only be 0 or 1.
• Abstraction that humans understand • Apply the rules of Boolean algebra
• Simplifies circuit design
Continuous to Discrete Conversion
• Voltage range 5 to 2 VDC
• Voltage range 0 to 0.8 VDC
• Less than 2 VDC and greater than 0.8 VDC
• Unstable and not reliable.
Invalid (Forbidden Zone)
Why is a range of values acceptable? Give an example, not related to voltage?
Component Properties
Propagation delay
NOT Gate: Closer Inspection
Output (Y) transitions from logic 0
Ideal Property
Real Property
Instantaneous transition from
0-to-1 and 1-to-0 Y
Delayed transition from 0-to-1 and 1-to-0
Gate Delay
Output (Y) transitions from logic 0
Real Property
tlh = 0-to-1 (low to high) time delay thl= 1-to-0 (high to low) time delay
The amount of time (in seconds) needed for the output value to change (propagation delay, td)
In this course, we’ll assume: td = tlh = thl
Forbidden zone
FA Component Analysis
Assume, propagation delay (td) for each logic gate is 1 nanosecond (ns).
• When the gate output changes 0-to-1 (or 1-to-0) one ns is required for the output to become stable.
Sum bit analysis
Assume Ci, A, B, S are all initially 0
New Input Value
Sum bit analysis (continued)
Assume Ci, A, B, S are all initially 0
New Input Value
Sum bit analysis (continued)
Assume Ci, A, B, S are all initially 0
New Input Value
Sum bit analysis (continued)
Assume Ci, A, B, S are all initially 0
New Input Value
MOS pull-up and pull-down transistor networks are not changing, so the output does not change (even though the inputs have changed)
Sum bit analysis (continued)
Assume Ci, A, B, S are all initially 0
New Input Value
Sum bit analysis (continued)
Assume Ci, A, B, S are all initially 0
New Input Value
MOS pull-up and pull-down transistor networks are not changing, so the output is not changing (even though the inputs have changed)
Sum bit analysis (continued)
Assume Ci, A, B, S are all initially 0
New Input Value
Sum bit analysis (continued)
Assume Ci, A, B, S are all initially 0
New Input Value
Sum bit: Worst case analysis
Sum bit is guaranteed to be stable in 2 ns.
In general, follow the longest path from output (S) to inputs and add the gate delays
• Easier than analyzing every possible input combination!
Carry-out bit: Worst Case Analysis
Carry-out bit is guaranteed to be stable in 3 ns.
Programming Help
FA Component: Worst Case Analysis
max( Sum td, Carry-out td)
• All component outputs will be stable in 3 ns Diag.
CO CI A FA B
Programming Help, Add QQ: 749389476